Radio frequency switch

ABSTRACT

A switch that selectively changes radio frequency signals includes at least three FETs, which are connected in series. The source electrodes or drain electrodes arranged at an intermediate stage have a width narrower than that of the source electrodes or the drain electrodes arranged at the initial and final stages. It is thus possible to lower the parasitic capacitance to ground at the intermediate stage and to thereby realize the switch having a high handling power.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to a radio frequency (RF) switch that is used for a radio frequency device such as a mobile telecommunications device, and more particularly, to the radio frequency switch on which multiple FETs are connected in series.

2. Description of the Related Art

In recent years, an RF switch having multiple ports (SPNT: Single Pole N-Through: N denotes the number of ports) has been employed in a mobile telephone unit, which communicates over multiple carrier signals. The RF switch includes a field-effect transistor (FET) composed of compound semiconductors. The RF switch is required to have a low harmonic performance, more specifically −70 dBc or less, to a fundamental harmonic of a transmitting signal. In order to suppress a harmonic component at a low level, the FET is required to improve linearity in the on-state resistance and to have an excellent off-state power.

In order to improve the off-state power, commonly, the FETs are connected in series at M stages. FIG. 1 shows an example of FETs connected in series at M stages. In the case where all the FETs are off, an RF signal passes through an RF signal line. In the case where all FETs are on, the RF signal passes across the FETs to the ground. In the case where all the FETs connected in series at M stages are off, each stage receives a voltage of 1/M theoretically. If the voltage of the RF signal is denoted by V, the voltage of V/M is applied to each of the FETs. However, in fact, each FET is affected by a parasitic capacitance to ground of the FET, which is denoted by Cp in FIG. 2. Referring to FIG. 2, Cds denotes a capacitance between the drain and source of each FET, and Cg denotes a capacitance between the gate and source or between the gate and drain of each FET. Referring to FIG. 3A, an impedance Zcp of the parasitic capacitance Cp to ground is connected to the impedance Z of the FET at each stage. Accordingly, as shown in FIG. 3B, the impedance at each stage is not equal (Z→Z′ (<Z)). Because of the aforementioned impedance inequality among the stages, a voltage V1 is applied to the FET (the impedance Z) closest (or directly connected) to the RF signal line, in which the voltage V1 is greater than a voltage V2 (<V1) applied to the other stages (impedance Z′ (<Z). This results in a problem in that a handling power becomes smaller than a value calculated from the following logical formula 1. Pmax=2[M(Vp−Vcont)]² /Zo  (Formula 1)

Here, M denotes the number of stages of the series connection, Vp denotes a pinch-off voltage at which the FET turns off from on or vise versa, Vcont is a control voltage applied to the gate of the FET, Zo is a system impedance, and Pmax is the maximum handling power.

In order to solve the aforementioned problem, as shown in FIG. 4, Mitchell B. Shifrin, et al. propose to add capacitances C1 and C2 to the stages to thus modify the parasitic capacitance to ground (see Mitchell B. Shifrin, et al., “Monolithic FET structures for High-Power Control Component Applications”, IEEE Transactions on Microwave Theory and Technique, Vol. 37, No. 12, December 1989, pp. 2134-2141 (hereinafter referred to as Document 1)). By connecting the capacitances C1 and C2 in parallel with the FET, the impedance is equally divided at each stage and the high-frequency voltage V is equally divided into V1, V2, and V3. (V1=V2=V3).

Referring to FIGS. 5A and 5B, Japanese Patent Application Publication No. 7-70245 (hereinafter referred to as Document 2) and Japanese Patent Application Publication No. 9-8621 (hereinafter referred to as Document 3) disclose that a capacitance, Ca in FIG. 5A and another capacitance Cb in FIG. 5B, are respectively added between the source or drain and the gate, and the voltage divided between the gate and source is intentionally shifted. FIG. 6A shows changes of a voltage difference between V1 and V2 (V1−V2) and another voltage difference between V2 and V3 (V2−V3) in a case where the capacitances Ca and Cb are not added. FIG. 6B shows FIG. 6A shows changes of the voltage difference (V1−V2) and the voltage difference (V2−V3) in a case where the capacitances Ca and Cb are added as shown in FIGS. 5A and 5B. Here, V1 is the voltage of the RF signal, V2 is the voltage at a connection point between the capacitance Ca and the gate, and V3 is the voltage at a node that connects the two FETs in series. A symbol Vp in FIGS. 6A and 6B denotes the pinch-off voltage. The use of the additional capacitances Ca and Cb shifts the voltage divided between the gate and source. Even if the RF voltage has a large amplitude, the voltage can be offset so that the gate voltage may not exceed the pinch-off voltage Vp. Thus, the handling power is improved.

However, the conventional technique disclosed in Document 1 and shown in FIG. 4 has a problem in which a signal is leaked through the capacitances C1 and C2. This leakage current degrades isolation at the time of switching off. Costs are increased in the capacitance formation process. In addition, in case where the capacitances C1 and C2 have a low breakdown voltage, the surge resistance such as ESD may be degraded. Generally, a capacitance on an MMIC has a low breakdown voltage.

The conventional techniques disclosed in Documents 2 and 3, shown in FIGS. 5A and 5B, also have the same problem as that in Document 1. Additionally, there is still another problem in that the FETs are required to have a high breakdown voltage, as compared to the circuit without the capacitances Ca and Cb.

Further, in recent years HEMT has been used instead of MESFET in order to reduce the insertion loss of the switch. Generally, when the on-state resistance is lowered, the breakdown voltage tends to be lowered due to a highly concentrated channel layer. Therefore, it is no longer possible to solve the above-mentioned problems with the conventional techniques disclosed in Documents 1 through 3, which have the problems in terms of the breakdown voltages.

SUMMARY OF THE INVENTION

It is a general object of the present invention to solve the above-mentioned problems and provide a radio frequency switch. More specifically, the voltage applied to the FETs connected in series in the off state is equally divided, and the handling power is improved easily and at a low cost.

According to an aspect of the present invention, preferably, there is provided a switch comprising at least three FETs that are connected in series and select one of radio frequency signals, and one of the at least three FETs arranged at an intermediate stage having a width of a source or drain electrode narrower than widths of source or drain electrodes of other FETs arranged at initial and final stages. It is thus possible to reduce the parasitic capacitance to ground at the intermediate stage and thereby realize the improved handling power readily and at a low cost with the off-FETs connected in series.

On the above-mentioned configuration, the radio frequency switch comprises at least four FETs connected in series. Ones of the at least four FETs arranged on intermediate stages having widths of source or drain electrodes narrower than those of the source or drain electrodes arranged at the initial and final stages. Preferably, a total width of gate electrodes of the FETs except those arranged at the initial and final stages is smaller than that of gate electrodes of the FETs arranged at the initial and final stages. In addition, the above-mentioned configuration may further include electrode lines that extend along gate electrodes of the at least three FETs, and the electrode lines of the FETs except those arranged at the initial and final stages is shorter than that of the electrode lines of the FETs arranged at the initial and final stages.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present invention will be described in detail with reference to the following drawings, wherein:

FIG. 1 shows an example of FETs connected in series at M stages;

FIG. 2 shows an equivalent circuit of an RF switch;

FIGS. 3A and 3B are circuit diagrams illustrating a parasitic capacitance to ground and a drawback because thereof;

FIG. 4 is a circuit diagram of a conventional RF switch that solves the drawback shown in FIGS. 3A and 3B;

FIG. 5 is another circuit diagram of the conventional RF switch that solves the drawback shown in FIGS. 3A and 3B;

FIGS. 6A and 6B are waveform diagrams llustrating operations of the RF switch shown in FIG. 5;

FIG. 7 is a plain view of an RF switch in accordance with a first embodiment of the present invention;

FIG. 8 is a graph describing a relationship between applied power and insertion loss observed in the first embodiment of the present invention in contrast to the prior art;

FIG. 9 is a plan view of an RF switch in accordance with a second embodiment of the present invention; and

FIG. 10 is a plain view of an RF switch in accordance with a third embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description will now be given, with reference to the accompanying drawings, of embodiments of the present invention.

First Embodiment

FIG. 7A is a plan view of an RF switch in accordance with a first embodiment of the present invention. The RF switch in FIG. 7A includes FETs connected in series at three stages. FIG. 7B shows a conventional RF switch having the FETs connected in series at three stages. As will be described below, the width of an electrode interconnection that is connected to a source or drain of the FET at an intermediate (second) stage is narrower than another electrode interconnection that is connected to the source or drain of the FET at an initial (first) stage and an RF line or that is connected to the source or drain of the FET at a final (third) stage and a ground line. The electrode interconnection that is connected to the source of the FET is referred to as a source electrode. The electrode interconnection that is connected to the drain of the FET is referred to as a drain electrode.

Three FETs 10 ₁, 10 ₂, and 10 ₃ are arranged in three separate FET-forming regions 16 ₁, 16 ₂, and 16 ₃ provided in a compound semiconductor substrate such as GaAs. The compound semiconductor substrate corresponds to a sheet of FIG. 7A. These FETs are referred to as an FET group 10. Each of the FETs 10 ₁, 10 ₂, and 10 ₃ connected in series in the FET-forming regions 16 ₁, 16 ₂, and 16 ₃ includes multiple FETs connected in parallel. There are seven FETs in each of the FET-forming regions 16 ₁, 16 ₂, and 16 ₃ as shown in FIG. 7A. The FETs 10 ₁, 10 ₂, and 10 ₃ are connected in series between an RF line 12 and a ground (GND) line 14. The FET 10 ₁ is directly connected to the RF line 12. The FET 10 ₃ is directly connected to the GND line 14. The FET 10 ₃ is connected between the FET 10 ₁ and the FET 10 ₃.

A source/drain electrode interconnection (hereinafter referred to as S/D electrode interconnection) 20 ₁ extends vertically on the FET-forming region 16 ₁ from the RF line 12. An S/D electrode interconnection 22 ₁ is arranged on the FET-forming region 16 ₁. A gate electrode interconnection 18 ₁ is arranged between the S/D electrode interconnections 20 ₁ and 22 ₁. The S/D electrode interconnections 20 ₁ and 22 ₁ respectively face the gate electrode interconnection 18 ₁ in the opposite directions. The S/D electrode interconnection 22 ₁ is connected to an S/D electrode interconnection 20 ₂, which is arranged on the FET-forming region 16 ₂ at the second stage, by way of a linkup electrode interconnection 24 ₁ that extends parallel to the RF line 12. The S/D electrode interconnection 20 ₂, the linkup electrode interconnection 24 ₁, and the S/D electrode interconnections 22 ₁ form a continuous interconnection pattern, which is connected to the source or drain of the FET 10 ₂ at the second stage in the series circuit of the three FETs. This continuous interconnection pattern including 22 ₁, 24 ₁, and 20 ₂ is indicated by a reference numeral 30 ₁.

An S/D electrode interconnection 22 ₂ and the S/D electrode interconnection 20 ₂ are arranged in the FET-forming region 16 ₂. A gate electrode interconnection 18 ₂ is arranged between the S/D electrode interconnections 20 ₂ and 22 ₂. The S/D electrode interconnections 20 ₂ and 22 ₂ respectively face the gate electrode interconnection 18 ₂ in opposite directions. The S/D electrode interconnection 22 ₂ is connected to an S/D electrode interconnection 20 ₃ that is arranged in the FET-forming region 16 ₃ at the third stage, by way of a linkup electrode interconnection 24 ₂ that extends parallel to the RF line 12. The S/D electrode interconnection 22 ₂, the linkup electrode interconnection 24 ₂, and the S/D electrode interconnections 20 ₃ are a continuous interconnection pattern, which is connected to source or drain of the FET 10 ₂ at the second stage of the series circuit. This continuous interconnection pattern including 22 ₂, 24 ₂, and 20 ₃ is indicated by a reference numeral 30 ₂.

An S/D electrode interconnection 22 ₃ and the S/D electrode interconnection 20 ₃ are arranged on the FET-forming region 16 ₃. The S/D electrode interconnection 22 ₃ extends from the GND line 14. A gate electrode interconnection 18 ₃ is arranged between the S/D electrode interconnections 20 ₃ and 22 ₃. The S/D electrode interconnections 20 ₃ and 22 ₃ respectively face the gate electrode interconnection 18 ₃ in opposite directions.

In accordance with the first embodiment of the present invention, the parasitic capacitance Cp to ground is reduced by making the electrode interconnections thin. The electrode interconnections generate the parasitic capacitance Cp to ground. As shown in an equivalent circuit in FIG. 2, the parasitic capacitance Cp to ground, which brings inequality in applied voltages, corresponds to the drain or source at the second stage in the series-connected circuit. The electrodes connected to the RF line 12 or the ground line 14 are not involved in the inequality in applied voltages. The first embodiment of the present invention focuses on this point. The widths of the S/D electrode interconnections 30 ₁ and 30 ₂ are thinner than those of the S/D electrode interconnections 20 ₁ and 22 ₃. The S/D electrode interconnections 30 ₁ and 30 ₂ are connected to the source or drain at the second stage. The S/D electrode interconnection 20 ₁ is connected to source or drain of the FET 10 ₁ and the RF line 12 at the first stage. The S/D electrode interconnection 22 ₃ is connected to the source or drain of the FET 10 ₃ and the GND line 14 at the third stage.

A condition such that Wc is smaller than Wb (Wc<Wb) where Wc denotes the widths of the S/D electrode interconnections 30 ₁ and 30 ₂, and Wc denotes the widths of the S/D electrode interconnections 20 ₁ and 22 ₃. FIG. 8 shows values of input power (dBm) and insertion loss (dB) actually measured under the condition such that Wc is 2 μm and Wb is 5 μm. FIG. 7B is a plan view of a comparative conventional RF switch in which all the S/D electrode interconnections have an identical width Wa of 3 μm. For comparison, FIG. 8 also shows the FET characteristics of the conventional RF switch in FIG. 7B. Referring to FIG. 8, if the insertion loss is degraded by 0.1 dB, the applied power is 35 dBm in the conventional circuit. In contrast, the first embodiment of the present invention achieves an approximately 2 dB improvement since the insertion loss is degraded by 0.1 dB for an applied power of 37 dBm.

As described above, it is thus possible to realize the RF switch having an improved high handling power, by lowering the parasitic capacitance Cp to ground without costly additional capacitances and degrading the surge resistance.

Referring back to FIG. 7A, the S/D electrode interconnections 30 ₁ and 30 ₂ have the identical width Wc. Alternatively, the linkup electrode interconnection 24 ₁ and 24 ₂ may be slightly thicker than those of the other S/D electrode interconnections. That is, the S/D electrode interconnections 30 ₁ and 30 ₂ may have different widths. The parasitic capacitance Cp to ground can be reduced as long as the S/D electrode interconnections 30 ₁ and 30 ₂ have areas smaller than those in the conventional circuit.

The present invention is not limited to the three-stage series circuit shown in FIG. 7A, but an arbitrary number of stages may be employed. For instance, a five-stage series circuit may be employed in which the S/D electrode interconnections at the second through fourth stages have the width Wc and those at the first and fifth stages connected to the RF line and GND line have the width Wb (Wc<Wb).

Second Embodiment

FIG. 9 is a plan view of an RF switch in accordance with a second embodiment of the present invention. Hereinafter, in the second embodiment, the same components and configurations as those of the first embodiment have the same reference numerals. In accordance with the second embodiment of the present invention, the total gate width of the FETs that are arranged in the FET-forming regions 16 ₂ at the intermediate (second in the present embodiment) stage(s) is configured to be smaller than the total gate width of the FETs at the initial and final stages. More specifically, each of the FET-forming regions 16 ₁ and 16 ₃ includes seven FETs. In contrast, the FET-forming region 16 ₂ includes six FETs. It is thus possible to reduce the total area of the S/D electrode interconnections 30 ₁ and 30 ₂, as compared to that in the circuit shown FIG. 7A, and to thereby further reduce the parasitic capacitance Cp to ground. This makes it possible to realize the RF switch having a higher handling power, by lowering the parasitic capacitance Cp to ground without costly additional capacitances and degrading the surge resistance.

Third Embodiment

FIG. 10 is a plain view of an RF switch in accordance with a third embodiment of the present invention. Hereinafter, in the second embodiment, the same components and configurations as those of the first embodiment have the same reference numerals. The third embodiment has an arrangement in which the FETs arranged in the FET-forming regions 16 ₂ at the second (intermediate) stage have a size smaller than that of the FETs at the first and third stage. It is thus possible to further reduce the parasitic capacitance Cp to ground, by shortening the total length of the S/D electrode interconnections 30 ₁ and 30 ₂. This makes it possible to realize the RF switch having a higher handling power, by lowering the parasitic capacitance Cp to ground without costly additional capacitances and degrading the surge resistance. The third embodiment may be combined with the second embodiment of the present invention.

The present invention is not limited to the above-mentioned embodiments, and other embodiments, variations and modifications may be made without departing from the scope of the present invention.

The present invention is based on Japanese Patent Application No. 2004-009878 filed on Jan. 16, 2004, the entire disclosure of which is hereby incorporated by reference. 

1. A switch comprising at least three FETs that are connected in series and select one of radio frequency signals, one of the at least three FETs arranged at an intermediate stage having a width of a source or drain electrode narrower than widths of source or drain electrodes of other FETs arranged at initial and final stages.
 2. The switch as claimed in claim 1, wherein the radio frequency switch comprises at least four FETs connected in series.
 3. The switch as claimed in claim 2, wherein ones of the at least four FETs arranged on intermediate stages having widths of source or drain electrodes narrower than those of the source or drain electrodes arranged at the initial and final stages.
 4. The switch as claimed in claim 1, wherein a total width of gate electrodes of the FETs except those arranged at the initial and final stages is smaller than that of gate electrodes of the FETs arranged at the initial and final stages.
 5. The switch as claimed in claim 1, further comprising electrode lines that extend along gate electrodes of the at least three FETs, wherein the electrode lines of the FETs except those arranged at the initial and final stages is shorter than that of the electrode lines of the FETs arranged at the initial and final stages. 